Optimization of semiconductor devices continues to be an important goal for the semiconductor industry. The continued miniaturization of semiconductor devices, such as bipolar transistors, presents ongoing challenges to semiconductor manufacturers in maintaining or improving that optimization while maintaining product yields and minimizing production time and costs. One such challenge resides in reducing the high collector resistance associated with bipolar transistors, such as vertical PNP (VPNP) bipolar transistors. The collector resistance limits the minimum saturation voltage (Vcesat) of the VPNP transistor. Minimum Vcesat is desired for maximum headroom and lower power consumption of a transistor. Further, this higher resistance is undesirable because it can adversely affect device speed and overall device performance, and as device sizes continue to shrink, this resistance will have even a greater impact.
Accordingly, there is a need to provide a process and device by which the resistance can be reduced in a bipolar transistor without affecting other components that might be present in the device.